With silicon (Si) wafers, epitaxial growth of different semiconductor materials having different lattice constants and thermal coefficients results in the generation of defects, such as dislocation defects which in turn lead to poor transistor performance and reliability issues. Substrates with SRB layers, including gallium arsenide (GaAs) or silicon germanium (SiGe) stepped or graded, are useful in achieving stress relaxation. However, the SRB layers are thick (e.g., ranging between 2 μm to 2.5 μm) and therefore expensive. Further, if an intermediate chemical mechanical polishing (CMP) step is used to planarize the layer and smoothen the surface roughness, there is a risk of having oxide residues on top before next epi step. Dielectric residues would than degrade the quality of the top epi layer.
A need therefore exists for methodology enabling the application of a thin SRB layer which achieves complete stress relaxation and locally confines defects at the bottom of trenches on a textured Si surface and the resulting device.